LR4102 Datasheet

PDF预览

• 1
• 2
• 3
• 4
• 5
• 6
• 7
• 8
• 9
• 10
• 11
• 12
• 13
• 14
• 15
• 16
• 17
• 18
• 19
• 20
• 21
• 22
• 23
• 24
• 25
• 26
• 27
• 28
• 29
• 30
• 31
• 32

TinyRISC

庐

LR4102

Microprocessor

Datasheet

The TinyRISC LR4102 Microprocessor is a compact, high performance

32-bit microprocessor implemented in the LSI Logic G11鈩?technology.

The LR4102 is a complete microprocessor solution with caches, an

external bus interface with built-in memory controllers, and on-chip

debug. The LR4102 is built using the EZ4102 EasyMACRO subsystem,

available to customers through the LSI Logic CoreWare

庐

program.

The LR4102 provides a 32-bit FBusMACRO to control all off-chip data

transactions (including DRAM or SDRAM) and an EJTAG interface for

on-chip debug with PC trace output.

Figure 1

illustrates the LR4102 chip.

Figure 1

LR4102

LR4102 Block Diagram

MMU

TLB RAM

Caches

Clock

Controller

32-bit TinyRISC

4102 CPU

and FastMDU

BIU and Cache

Controller (BBCC)

OCM

FBus-

MACRO

FBus

Two 32-bit Timers

SerialICE鈩?1 Port

EJTAG

SerialICE-1

Interface

EJTAG

Interface

EJTAG

Extended Debug MACRO

PC Trace

Output

The LR4102 microprocessor is powered by either 2.5 V (for 85 MHz

operation) or 1.8 V (for 50 MHz operation). The chip I/O ring requires

3.3 V. With a system clock of 85 MHz, peak performance is 85 MIPS and

sustained performance is estimated at 68 MIPS. With a 50 MHz clock,

performance is 50 MIPS peak and 40 MIPS sustained.

March 2000

Copyright 漏 1998鈥?000 by LSI Logic Corporation. All rights reserved.

1

next

LR4102相关型号PDF文件下载

• 型号
  版本
  描述
  厂商
  下载
• LR4102
  英文版
  LSI Computer Systems [Microprocessor]
  LSI
  LR4102
• LR4173
  英文版
  Telecommunication IC
  ETC
  LR4173
• LR4174
  英文版
  Telecommunication IC
  ETC
  LR4174

您可能感兴趣的PDF文件资料

• LR4174
• LR4173
• LR4102

热门IC型号推荐

• LP2305LT1G
• LAN8710AI-EZK-TR
• LP3878SD-1.0
• LM3460M5X-1.5
• LT1129CQ-3.3
• LTC1485CS8
• LM2940CT-12
• L6562DTR
• LM4041DIM3X-ADJ
• LM4889ITLX
• LM2931AZ-5.0
• LTC1754ES6-5#TR