鈥?/div>
265 ps Propagation Delay
5 ps Skew Between Outputs
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V with V
EE
=
鈭?.2
V to
鈭?.7
V
Internal Input Pulldown Resistors
Pb鈭扚ree Packages are Available
8
HL11
ALYWG
G
8
KL11
ALYWG
G
1
Q
0
1
8
V
CC
4Q M
G
G
Q
0
2
7
D
DFN8
MN SUFFIX
CASE 506AA
1
4
1
Q
1
3
6
D
Q
1
4
5
V
EE
H = MC10
K = MC100
4Q = MC10
2E = MC100
A = Assembly Location
L
Y
W
M
G
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb鈭扚ree Package
Figure 1. Logic Diagram and Pinout Assignment
Table 1. PIN DESCRIPTION
PIN
D, D
Q0, Q0; Q1, Q1
V
CC
V
EE
EP
FUNCTION
ECL Data Inputs
ECL Data Outputs
Positive Supply
Negative Supply
Exposed pad must be connected to a
sufficient thermal conduit. Electrically
connect to the most negative supply or
leave floating open.
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
December, 2006鈭?Rev. 9
1
Publication Order Number:
MC10EL11/D
2E M
G
G
4