MC100EL38
5V ECL
梅2, 梅4/6
Clock
Generation Chip
The MC100EL38 is a low skew
梅2, 梅4/6
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
http://onsemi.com
either a differential or single-ended ECL or, if positive power supplies
are used, PECL input signal.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
SO鈭?0 WB
to 0.5 mA. When not used, V
BB
should be left open.
DW SUFFIX
CASE 751D
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
MARKING DIAGRAM*
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
20
could lead to losing synchronization between the internal divider
stages. The internal enable flip鈭抐lop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
100EL38
AWLYYWWG
referenced to the negative edge of the clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
the
梅2
and the
梅4/6
outputs are both transitioning from a LOW to a
1
HIGH. This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state;
A
= Assembly Location
therefore, for systems which utilize multiple EL38s, the master reset
WL
= Wafer Lot
YY
= Year
(MR) input must be asserted to ensure synchronization. For systems
WW
= Work Week
which only use one EL38, the MR pin need not be exercised as the
G
= Pb鈭扚ree Package
internal divider design ensures synchronization between the
梅2
and
the
梅4/6
outputs of a single device.
*For additional marking information, refer to
鈥?/div>
50 ps Output-to-Output Skew
Application Note AND8002/D.
鈥?/div>
Synchronous Enable/Disable
鈥?/div>
Master Reset for Synchronization
ORDERING INFORMATION
鈥?/div>
ESD Protection: > 2 kV Human Body Model,
See detailed ordering and shipping information in the package
> 100 V Machine Model
dimensions section on page 6 of this data sheet.
鈥?/div>
The 100 Series Contains Temperature Compensation
鈥?/div>
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
鈥?/div>
Moisture Sensitivity Level 1
with V
EE
= 0 V
For Additional Information, see Application Note
AND8003/D
鈥?/div>
NECL Mode Operating Range: V
CC
= 0 V with
鈥?/div>
Flammability Rating: UL 94 V鈭? @ 0.125 in,
V
EE
=
鈭?.2
V to
鈭?.7
V
Oxygen Index: 28 to 34
鈥?/div>
Internal 75 kW Input Pulldown Resistors on CLK, EN,
鈥?/div>
Transistor Count = 388 devices
MR, and DIVSEL
鈥?/div>
Q Output will Default LOW with Inputs Open or at
鈥?/div>
Pb鈭扚ree Packages are Available*
V
EE
鈥?/div>
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
October, 2006
鈭?/div>
Rev. 7
1
Publication Order Number:
MC100EL38/D
MC100EL38DWG 产品属性
38
集成电路 (IC)
时钟/计时 - 时钟发生器，PLL，频率合成器
100EL
时钟发生器
无
NECL，PECL
ECL
1
1:4
是/是
1.2GHz
是/无
±4.2 V ~ 5.7 V
-40°C ~ 85°C
表面贴装
20-SOIC（0.295"，7.50mm 宽）
20-SOIC
管件
MC100EL38DWGOS
1
2
3
4
5
6
7
