MC100LVELT23D Datasheet

  • MC100LVELT23D

  • 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

  • 70.59KB

  • 8页

  • ONSEMI

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MC100LVELT23
3.3 V Dual Differential
LVPECL/LVDS to LVTTL
Translator
The MC100LVELT23 is a dual differential LVPECL/LVDS to
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels
are used only +3.3 V and ground are required. The small outline 8-lead
package and the dual gate design of the LVELT23 makes it ideal for
applications which require the translation of a clock and a data signal.
The LVELT23 is available in only the ECL 100K standard. Since
there are no LVPECL outputs or an external V
BB
reference, the
LVELT23 does not require both ECL standard versions. The LVPECL
inputs are differential. Therefore, the MC100LVELT23 can accept any
standard differential LVPECL input referenced from a V
CC
of +3.3 V.
http://onsemi.com
MARKING
DIAGRAMS*
8
SOIC鈭?
D SUFFIX
CASE 751
KVT23
ALYW
1
8
8
1
TSSOP鈭?
DT SUFFIX
CASE 948R
1
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
KR23
ALYW
8
1
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2.0 ns Typical Propagation Delay
Maximum Frequency > 180 MHz
Differential LVPECL Inputs
PECL Mode Operating Range:V
CC
= 3.0 V to 3.8 V
with GND = 0 V
24 mA LVTTL Outputs
Flow Through Pinouts
Internal Pulldown and Pullup Resistors
Pb鈭扚ree Package is Available
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Semiconductor Components Industries, LLC, 2005
1
February, 2005 鈭?Rev. 12
Publication Order Number:
MC100LVELT23/D

MC100LVELT23D 产品属性

  • ON Semiconductor

  • 转换 - 电压电平

  • LVDS/LVPECL to LVTTL

  • 2.5 ns

  • 3.8 V

  • 3 V

  • + 85 C

  • SMD/SMT

  • SOIC-8

  • - 40 C

  • Tube

  • 98

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