Power Dissipation, per Package鈥?/div>
Storage Temperature
mA
mW
Tstg
鈥?65 to + 150
260
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = 鈥?55掳 to 125掳C for all packages.
_
C
_
C
BLOCK DIAGRAM
7
6
3
5
J
C
K
R
Q
2
S
Q
1
Lead Temperature (8鈥揝econd Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
鈥燭emperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic 鈥淟鈥?Packages: 鈥?12 mW/
_
C From 100
_
C To 125
_
C
TRUTH TABLE
Inputs
C鈥?/div>
J
1
X
0
X
1
X
X
X
X
X
X
X
K
X
0
X
1
1
X
X
X
X
S
0
0
0
0
0
0
1
0
1
R
0
0
0
0
0
0
0
1
1
Qn鈥?/div>
0
1
0
1
Qo
X
X
X
X
Outputs*
Qn+1
1
1
0
0
Qo
Qn
1
0
1
Qn+1
0
0
1
1
Qo
Qn
0
1
1
No
Change
4
9
10
13
11
12
VDD = PIN 16
VSS = PIN 8
J
C
K
R
Q
14
S
Q
15
X = Don鈥檛 Care
鈥?= Level Change
鈥?= Present State
* = Next State
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS
鈮?/div>
(Vin or Vout)
鈮?/div>
VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
漏
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14027B
107
1
2
3
4
5
6
