MC14522BCL Datasheet_PDF文件下载_芯片资料查询

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Presettable 4-Bit Down Counters

The MC14522B BCD counter and the MC14526B binary counter are

constructed with MOS P鈥揷hannel and N鈥揷hannel enhancement mode

devices in a monolithic structure.

These devices are presettable, cascadable, synchronous down counters

with a decoded 鈥?鈥?state output for divide鈥揵y鈥揘 applications. In single stage

applications the 鈥?鈥?output is applied to the Preset Enable input. The

Cascade Feedback input allows cascade divide鈥揵y鈥揘 operation with no

additional gates required. The Inhibit input allows disabling of the pulse

counting function. Inhibit may also be used as a negative edge clock.

These complementary MOS counters can be used in frequency synthesiz-

ers, phase鈥搇ocked loops, and other frequency division applications requiring

low power dissipation and/or high noise immunity.

鈥?/div>

Supply Voltage Range = 3.0 Vdc to 18 Vdc

鈥?/div>

Logic Edge鈥揅locked Design 鈥?Incremented on Positive Transition of

Clock or Negative Transition of Inhibit

鈥?/div>

Asynchronous Preset Enable

鈥?/div>

Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS*

(Voltages Referenced to VSS)

Symbol

VDD

Parameter

DC Supply Voltage

Value

MC14522B

MC14526B

L SUFFIX

CERAMIC

CASE 620

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦

Unit

V

鈥?0.5 to + 18.0

卤

10

500

鈥?65 to + 150

260

Vin, Vout

Iin, Iout

PD

Tstg

TL

Input or Output Voltage (DC or Transient)

鈥?0.5 to VDD + 0.5

Input or Output Current (DC or Transient),

per Pin

Power Dissipation, per Package鈥?/div>

Storage Temperature

Lead Temperature (8鈥揝econd Soldering)

mA

mW

ORDERING INFORMATION

MC14XXXBCP

MC14XXXBCL

MC14XXXBDW

Plastic

Ceramic

SOIC

TA = 鈥?55掳 to 125掳C for all packages.

PIN ASSIGNMENT

Q3

P3

PE

INHIBIT

P0

CLOCK

Q0

VSS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDD

Q2

P2

CF

鈥?鈥?/div>

P1

RESET

Q1

_

C

_

C

* Maximum Ratings are those values beyond which damage to the device may occur.

鈥燭emperature Derating:

Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/

_

C From 65

_

C To 125

_

C

Ceramic 鈥淟鈥?Packages: 鈥?12 mW/

_

C From 100

_

C To 125

_

C

FUNCTION TABLE

Inputs

Clock

X

L

H

Reset

H

L

Inhibit

X

H

L

Preset

Enable

L

H

X

H

L

Cascade

Feedback

L

H

X

L

Output

鈥?鈥?/div>

L

H

L

Resulting

Function

Asynchronous reset*

Asynchronous reset

Asynchronous preset

Decrement inhibited

No change** (inactive edge)

Decrement**

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high鈥搃mpedance circuit. For proper

operation, Vin and Vout should be constrained

to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

v

X = Don鈥檛 Care

NOTES:

* Output 鈥?鈥?is low when reset goes high only it PE and CF are low.

** Output 鈥?鈥?is high when reset is low, only if CF is high and count is 0000.

REV 3

1/94

漏

MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995

MC14522B MC14526B

1

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