MM74HC04 Hex Inverter
September 1983
Revised January 2005
MM74HC04
Hex Inverter
General Description
The MM74HC04 inverters utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits.
The MM74HC04 is a triple buffered inverter. It has high
noise immunity and the ability to drive 10 LS-TTL loads.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 8 ns
s
Fan out of 10 LS-TTL loads
s
Quiescent power consumption: 10
碌
W maximum at
room temperature
s
Low input current: 1
碌
A maximum
Ordering Code:
Order Number
MM74HC04M
MM74HC04M_NL
MM74HC04SJ
MM74HC04MTC
MM74HC04MTC_NL
MM74HC04N
MM74HC04N_NL
M14D
MTC14
MTC14
N14A
N14A
Package
Number
M14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
1 of 6 Inverters
Top View
漏 2005 Fairchild Semiconductor Corporation
DS005069
www.fairchildsemi.com
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