MM74HC573 3-STATE Octal D-Type Latch
September 1983
Revised May 2000
MM74HC573
3-STATE Octal D-Type Latch
General Description
The MM74HC573 high speed octal D-type latches utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
When the LATCH ENABLE(LE) input is HIGH, the Q out-
puts will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the out-
puts until LATCH ENABLE returns HIGH again. When a
HIGH logic level is applied to the OUTPUT CONTROL OC
input, all outputs go to a HIGH impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
The 74HC logic family is speed, function and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 18 ns
s
Wide operating voltage range: 2 to 6 volts
s
Low input current: 1
碌
A maximum
s
Low quiescent current: 80
碌
A maximum (74HC Series)
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number
MM74HC573WM
MM74HC573SJ
MM74HC573MTC
MM74HC573N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Truth Table
Output
Control
L
L
L
H
Latch
Enable
H
H
L
X
H
L
X
X
H
L
Q
0
Z
Data
Output
H
=
HIGH Level
L
=
LOW Level
Q
0
=
Level of output before steady-state input conditions were established.
Z
=
High Impedance
X
=
Don't Care
Top View
漏 2000 Fairchild Semiconductor Corporation
DS005212
www.fairchildsemi.com
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