MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
September 1983
Revised January 2005
MM74HC74A
Dual D-Type Flip-Flop with Preset and Clear
General Description
The MM74HC74A utilizes advanced silicon-gate CMOS
technology to achieve operating speeds similar to the
equivalent LS-TTL part. It possesses the high noise immu-
nity and low power consumption of standard CMOS inte-
grated circuits, along with the ability to drive 10 LS-TTL
loads.
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q outputs. The logic level present at the
data input is transferred to the output during the positive-
going transition of the clock pulse. Preset and clear are
independent of the clock and accomplished by a low level
at the appropriate input.
The 74HC logic family is functionally and pinout compatible
with the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to V
CC
and ground.
Features
s
Typical propagation delay: 20 ns
s
Wide power supply range: 2鈥?V
s
Low quiescent current: 40
碌
A maximum (74HC Series)
s
Low input current: 1
碌
A maximum
s
Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC74AM
MM74HC74AMX_NL
MM74HC74ASJ
MM74HC74AMTC
MM74HC74AMTCX_NL
MM74HC74AN
Package
Number
M14A
M14A
M14D
MTC14
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Inputs
PR
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
D
X
X
X
H
L
X
Q
H
L
H (Note 1)
H
L
Q0
Outputs
Q
L
H
H (Note 1)
L
H
Q0
鈫?/div>
鈫?/div>
L
Note:
Q0
=
the level of Q before the indicated input conditions were estab-
lished.
Note 1:
This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) level.
漏 2005 Fairchild Semiconductor Corporation
DS005106
www.fairchildsemi.com
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