MM74HCT573 鈥?MM74HCT574 Octal D-Type Latch 鈥?3-STATE Octal D-Type Flip-Flop
February 1990
Revised May 1999
MM74HCT573 鈥?MM74HCT574
Octal D-Type Latch 鈥?3-STATE Octal D-Type Flip-Flop
General Description
The
MM74HCT573
octal
D-type
latches
and
MM74HCT574 octal D-type flip-flop advanced silicon-gate
CMOS technology, which provides the inherent benefits of
low power consumption and wide power supply range, but
are LS-TTL input and output characteristic and pin-out
compatible. The 3-STATE outputs are capable of driving 15
LS-TTL loads. All inputs are protected from damage due to
static discharge by internal diodes to V
CC
and ground.
When the MM74HCT573 Latch Enable input is HIGH, the
Q outputs will follow the D inputs. When the Latch Enable
goes LOW, data at the D inputs will be retained at the out-
puts until Latch Enable returns HIGH again. When a high
logic level is applied to the Output Control input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the storage
elements.
The MM74HCT574 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
going transitions of the Clock (CK) input. When a high logic
level is applied to the Output Control (OC) input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the storage
elements.
The MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s
TTL input characteristic compatible
s
Typical propagation delay: 18 ns
s
Low input current: 1
碌A
maximum
s
Low quiescent current: 80
碌A
maximum
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Codes:
Order Number
MM74HCT573WM
MM74HCT573SJ
MM74HCT573MTC
MM74HCT573N
MM74HCT574WM
MM74HCT574SJ
MM74HCT574MTC
MM74HCT574N
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 1999 Fairchild Semiconductor Corporation
DS010627.prf
www.fairchildsemi.com
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