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MT48LC8M32B2TG Datasheet

  • MT48LC8M32B2TG

  • SYNCHRONOUS DRAM

  • 1200.70KB

  • 55页

  • MICRON

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PRELIMINARY
256Mb: x32
SDRAM
SYNCHRONOUS
DRAM
FEATURES
鈥?PC100 functionality
鈥?Fully synchronous; all signals registered on
positive edge of system clock
鈥?Internal pipelined operation; column address can
be changed every clock cycle
鈥?Internal banks for hiding row access/precharge
鈥?Programmable burst lengths: 1, 2, 4, 8, or full page
鈥?Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
鈥?Self Refresh Mode
鈥?64ms, 4,096-cycle refresh (15.6碌s/row)
鈥?LVTTL-compatible inputs and outputs
鈥?Single +3.3V 卤0.3V power supply
鈥?Supports CAS latency of 1, 2, and 3
MT48LC8M32B2 - 2 Meg x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/sdramds
Pin Assignment (Top View)
86-Pin TSOP
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE#
CAS#
RAS#
CS#
A11
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
OPTIONS
鈥?Configuration
8 Meg x 32 (2 Meg x 32 x 4 banks)
MARKING
8M32B2
TG
P
F5
1
B5
1
鈥?Package
86-pin TSOP (400 mil)
86-pin TSOP (400 mil) Lead-free
90-ball FBGA (8mm x 13mm)
90-ball FBGA (8mm x 13mm) Lead-free
鈥?Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
鈥?Operating Temperature Range
Commercial (0掳 to +70掳C)
Industrial (-40掳C to +85掳C)
NOTE:
1. Available on -7 only
Part Number Example:
-6
-7
None
IT
1
MT48LC8M32B2TG-7
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
Note:
The # symbol indicates signal is active LOW.
KEY TIMING PARAMETERS
SPEED
GRADE
-6
-7
CLOCK
ACCESS TIME
FREQUENCY
CL = 3*
166 MHz
143 MHz
5.5ns
6.0ns
SETUP
TIME
1.5ns
2ns
HOLD
TIME
1ns
1ns
8 Meg x 32
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
2 Meg x 32 x 4 banks
4K
4K (A0鈥揂11)
4 (BA0, BA1)
512 (A0鈥揂8)
*CL = CAS (READ) latency
09005aef80cd8e48
256MbSDRAMx32.p65 鈥?Rev. B; Pub. 03/04
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON鈥橲 PRODUCTION DATA SHEET SPECIFICATIONS.

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