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MTB52N06VL Datasheet

  • MTB52N06VL

  • TMOS POWER FET 52 AMPERES 60 VOLTS

  • 204.21KB

  • 10页

  • MOTOROLA   MOTOROLA

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MOTOROLA
Designer's
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB52N06VL/D
TMOS
Power Field Effect Transistor
D2PAK for Surface Mount
TMOS V is a new technology designed to achieve an on鈥搑esistance
area product about one鈥揾alf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E鈥揊ET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
鈥?/div>
On鈥搑esistance Area Product about One鈥揾alf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
鈥?/div>
Faster Switching than E鈥揊ET Predecessors
鈩?/div>
Data Sheet
V
鈩?/div>
MTB52N06VL
Motorola Preferred Device
N鈥揅hannel Enhancement鈥揗ode Silicon Gate
TMOS POWER FET
52 AMPERES
60 VOLTS
RDS(on) = 0.025 OHM
TM
D
G
S
CASE 418B鈥?2, Style 2
D2PAK
Features Common to TMOS V and TMOS E鈥揊ETs
鈥?/div>
Avalanche Energy Specified
鈥?/div>
IDSS and VDS(on) Specified at Elevated Temperature
鈥?/div>
Static Parameters are the Same for both TMOS V and TMOS E鈥揊ET
鈥?/div>
Surface Mount Package Available in 16 mm 13鈥搃nch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25掳C unless otherwise noted)
Rating
Drain鈥搕o鈥揝ource Voltage
Drain鈥搕o鈥揋ate Voltage (RGS = 1.0 M鈩?
Gate鈥搕o鈥揝ource Voltage 鈥?Continuous
鈥?Non鈥揜epetitive (tp
鈮?/div>
10 ms)
Drain Current 鈥?Continuous
鈥?Continuous @ 100掳C
鈥?Single Pulse (tp
鈮?/div>
10
碌s)
Total Power Dissipation
Derate above 25掳C
Total Power Dissipation @ TA = 25掳C (1)
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?STARTING TJ = 25掳C
(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 52 Apk, L = 0.3 mH, RG = 25
鈩?
Thermal Resistance 鈥?Junction to Case
鈥?Junction to Ambient
鈥?Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8鈥?from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
60
60
卤
15
卤
25
52
41
182
188
1.25
3.0
鈥?55 to 175
406
0.8
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/掳C
Watts
掳C
mJ
掳C/W
TJ, Tstg
EAS
R
胃JC
R
胃JA
R
胃JA
TL
掳C
Designer鈥檚 Data for 鈥淲orst Case鈥?Conditions
鈥?The Designer鈥檚 Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves 鈥?representing boundaries on device characteristics 鈥?are given to facilitate 鈥渨orst case鈥?design.
E鈥揊ET, Designer鈥檚, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 3
Motorola TMOS
漏
Motorola, Inc. 1996
Power
MOSFET Transistor Device Data
1

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