P2042A-08SR Datasheet

  • P2042A-08SR

  • LCD Panel EMI Reduction IC

  • 352.76KB

  • 8页

  • ALSC

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August 2005
rev 1.3
LCD Panel EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Provides up to 15dB of EMI suppression.
Generates a low EMI spread spectrum clock of the
input frequency.
Input frequency range: 30MHz to 110MHz.
Optimized for 32.5MHz, 54MHz, 65MHz and
108MHz pixel clock frequencies.
Internal loop filter minimizes external components
and board space.
Eight selectable high spread ranges up to 卤 1.9%.
SSON# control pin for spread spectrum enable and
disable options.
Low cycle-to-cycle jitter.
3.3V 卤 0.3V operating range.
Low power CMOS design.
Supports most mobile graphic accelerator and LCD
timing controller specifications.
Available in 8-pin SOIC and TSSOP Packages.
P2042A
wide reduction of EMI of
down stream clock and data
dependent signals. The P2042A allows significant system
cost savings by reducing the number of circuit board
layers ferrite beads,
regulations.
The P2042A uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented in a proprietary all digital method.
The P2042A modulates the output of a single PLL in
order to 鈥渟pread鈥?the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal鈥檚 bandwidth is called 鈥榮pread
spectrum clock generation鈥?
shielding and other passive
components that are traditionally required to pass EMI
Product Description
The P2042A is a versatile spread spectrum frequency
modulator designed specifically for digital flat panel
applications.
The
P2042A
reduces
electromagnetic
interference (EMI) at the clock source, allowing system
Applications
The P2042A is targeted towards digital flat panel
applications for notebook PCs, palm-size PCs, office
automation equipments and LCD monitors.
Block Diagram
VDD
SR0 CP1 CP0 SSON#
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive
鈥?/div>
Santa Clara, CA
鈥?/div>
Tel: 408.855.4900
鈥?/div>
Fax: 408.855.4999
鈥?/div>
www.alsc.com
Notice: The information in this document is subject to change without notice.

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