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S29C51004B12J Datasheet

  • S29C51004B12J

  • 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY

  • 298.16KB

  • 16页

  • ETC

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SyncMOS Technologies Inc.
S29C51004T/S29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY
Features
s
s
s
s
s
s
512Kx8-bit Organization
Address Access Time: 70, 90, 120 ns
Single 5V
卤
10% Power Supply
Sector Erase Mode Operation
16KB Boot Block (lockable)
1K bytes per Sector, 512 Sectors
鈥?Sector-Erase Cycle Time: 10ms (Max)
鈥?Byte-Write Cycle Time:
35
碌
s (Max)
Minimum 10,000 Erase-Program Cycles
Low power dissipation
鈥?Active Read Current: 20mA (Typ)
鈥?Active Program Current: 30mA (Typ)
鈥?Standby Current:
100
碌
A (Max)
Hardware Data Protection
Low V
CC
Program Inhibit Below 3.5V
Self-timed write/erase operations with end-of-cy-
cle detection
鈥?DATA Polling
鈥?Toggle Bit
CMOS and TTL Interface
Available in
one
versions
鈥?S29C51004T (Top Boot Block)
Description
The S29C51004T/S29C51004B is a high speed
524,288 x 8 bit CMOS flash memory. Writing or
erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, write enable WE, and output enable OE
controls to eliminate bus contention.
The S29C51004T/S29C51004B offers a combi-
nation of: Boot Block with Sector Erase/Write
Mode. The end of write/erase cycle is detected by
DATA Polling of I/O
7
or by the Toggle Bit I/O
6
.
TheS29C51004T/S29C51004B features a
sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.
Boot block architecture enables the device to
boot from a protected sector located either at the
top (S29C51004T) or the bottom (S29C51004B).
All inputs and outputs are CMOS and TTL
compatible.
The S29C51004T/S29C51004B is ideal for
applications that require updatable code and data
storage.
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Packages:
鈥?32-pin Plastic DIP
鈥?32-pin TSOP-I
鈥?32-pin PLCC
S29C51004T/S29C51004B
V1.0 May 2002
1

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