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SM5842 Datasheet

  • SM5842

  • Nippon Precision Circuits Inc [High-Class Audio Multi-funct...

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SM5842AP/APT
NIPPON PRECISION CIRCUITS INC.
High-Class Audio Multi-function Digital Filter
OVERVIEW
The SM5842AP/APT is a multi-function digital 铿乴ter
IC, fabricated using NPC鈥檚 Molybdenum-gate
CMOS process, for digital audio reproduction equip-
ment. It features 8-times oversampling (interpola-
tion), independent left and right-channel digital
deemphasis, and soft muting functions. It accepts 16,
18, 20 or 24-bit input data, and outputs data in 18,
20, 22 or 24-bit format. It operates using either a
384fs or 256fs system clock at sampling frequencies
up to 48 kHz + 10% (384fs SM5842AP, 384/256fs
SM5842APT).
s
s
s
s
s
鈥?256fs
- 13 MHz maximum frequency (at maximum
fs = 50.7 kHz, SM5842AP)
- 14.2 MHz maximum frequency (at maximum
fs = 55.2 kHz, SM5842APT)
Crystal oscillator circuit built-in
TTL-compatible input/outputs
5.0 卤 0.25 V supply
Molybdenum-gate CMOS process
28-pin plastic DIP
Filter Con铿乬uration
s
FEATURES
Functions
s
s
s
s
s
s
s
s
s
s
s
L/R 2-channel processing
8-times oversampling (interpolation)
鈥?/div>
鈮?/div>
卤0.00002 dB passband ripple
鈥?/div>
鈮?/div>
117 dB stopband attenuation
Digital deemphasis
鈥?32/44.1/48 kHz sampling frequency (fs)
鈥?2-channel independent ON/OFF control
Soft muting
鈥?2-channel independent ON/OFF control
Input data format
鈥?2s complement, MSB 铿乺st
- LR alternating, 16/18/20/24-bit serial, trail-
ing data
- LR alternating, 24-bit serial, leading data
- LR simultaneous, 24-bit serial, leading data
Output data format
鈥?2s complement, MSB 铿乺st, LR simultaneous
鈥?18/20/22/24-bit serial
鈥?BCKO burst (NPC format)
Dither round-up processing
鈥?ON (dither rounding)/OFF (normal rounding)
control
25-bit internal data length
Jitter-free function for correct operation in the
presence of jitter between the system clock and
LRCI clock
鈥?ON (jitter-free mode)/OFF (sync mode) control
256fs/384fs system clock selectable
鈥?384fs
- 21.2 MHz maximum frequency (at maximum
fs = 55.2 kHz)
s
s
Linear phase 3-stage FIR interpolation 铿乴ter
鈥?169-tap 1st stage (fs to 2fs)
鈥?29-tap 2nd stage (2fs to 4fs)
鈥?17-tap 3rd stage (4fs to 8fs)
Deemphasis 铿乴ter
- IIR 铿乴ter con铿乬uration for accurate gain and
phase characteristics
26
脳
24-bit parallel multiplier/32-bit accumulator
for high precision
Over铿俹w limiter built-in
APPLICATIONS
s
s
s
CD players
DAT players
PCM systems
PINOUT
DI / INF2N
BCKI
CKSLN
INF1N
IW1N / DIL
XTI
XTO
VSS
CKO
IW2N / DIR
OW1N
OW2N
SYNCN
RSTN
1
28
LRCI
DG
BCKO
WCKO
DOL
DOR
VDD
DITHN
MUTEL
MUTER
FSEL2
FSEL1
DEMPL
SM5842AP/APT
14
15
DEMPR
NIPPON PRECISION CIRCUITS鈥?

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