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PWRDN
REN
RCLK
LOCK
AV
CC
AGND
AGND
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R
OUT0
R
OUT1
R
OUT2
R
OUT3
R
OUT4
DV
CC
DGND
DV
CC
DGND
R
OUT5
R
OUT6
R
OUT7
R
OUT8
R
OUT9
description
The SN65LV1023A serializer and SN65LV1224A deserializer comprise a 10-bit serdes chipset designed to
transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz
to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload
encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC
patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,
the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is
available to place the output pins in the high-impedance state without losing PLL lock.
The SN65LV1023A and SN65LV1224A are characterized for operation over ambient air temperature of 鈥?40掳C
to 85掳C.
ORDERING INFORMATION
DEVICE
Serializer
Deserializer
PART NUMBER
SN65LV1023ADB
SN65LV1224ADB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
铮?/div>
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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