鈥?/div>
PECL-to-LVDS Translation
Data or Clock Signal Amplification
DESCRIPTION
The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater.
The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and
repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low
radiated emissions and minimal added jitter.
The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the
SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A
high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential
transmission lines with nominally 100-鈩?characteristic impedance.
Both devices provide a voltage reference (V
BB
) of typically 1.35 V below V
CC
for use in receiving single-ended
PECL input signals. When not used, V
BB
should be unconnected or open.
All devices are characterized for operation from -40掳C to 85掳C.
FUNCTION DIAGRAM
EN
A
B
V
CC
IN
GND
9
Scale = 50 ps/div
Y
Z
6
OUT
4
V
BB
Figure 1. SN65LVDS20 Output Eye Pattern With
4-Gbps PRBS Input
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Scale = 75 mV/div
7
Copyright 漏 2004鈥?005, Texas Instruments Incorporated