鈩?/div>
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 5 V, T
A
= 25掳C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (鈥?2-mA I
OH
, 64-mA I
OL
)
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Spacings
SN54ABT16541 . . . WD PACKAGE
SN74ABT16541A . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
description
The SN54ABT16541 and SN74ABT16541A are
noninverting 16-bit buffers composed of two 8-bit
sections with separate output-enable signals. For
either 8-bit buffer section, the two output-enable
(1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must
both be low for the corresponding Y outputs to be
active. If either output-enable input is high, the
outputs of that 8-bit buffer section are in the
high-impedance state.
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
V
CC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE2
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16541 is characterized for operation over the full military temperature range of 鈥?5掳C to 125掳C.
The SN74ABT16541A is characterized for operation from 鈥?0掳C to 85掳C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE1
L
L
H
X
OE2
L
L
X
H
A
L
H
X
X
OUTPUT
Y
L
H
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-螜螜B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
1997, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
1
1
2
3
4
5
6
7
8
9
10
