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SN74ALS138ADRG4 Datasheet

  • SN74ALS138ADRG4

  • 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

  • 523.65KB

  • 16页

  • TI

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SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E 鈥?APRIL 1982 鈥?REVISED JULY 1996
D
D
D
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
Incorporate Three Enable Inputs to Simplify
Cascading and /or Data Reception
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
SN54ALS138A, SN54AS138 . . . J PACKAGE
SN74ALS138A, SN74AS138 . . . D OR N PACKAGE
(TOP VIEW)
description
The
鈥睞LS138A
and
鈥睞S138
are 3-line to 8-line
decoders/demultiplexers designed for high-
performance memory-decoding or data-routing
applications requiring very short propagation
delay times. In high-performance systems, these
devices can be used to minimize the effects of
system decoding. When employed with
high-speed memories with a fast enable circuit,
the delay times of the decoder and the enable time
of the memory are usually less than the typical
access time of the memory. The effective system
delay introduced by the Schottky-clamped system
decoder is negligible.
A
B
C
G2A
G2B
G1
Y7
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54ALS138A, SN54AS138 . . . FK PACKAGE
(TOP VIEW)
C
G2A
NC
G2B
G1
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
B
A
NC
V
CC
Y0
Y1
Y2
NC
Y3
Y4
Copyright
漏
1996, Texas Instruments Incorporated
The conditions at the binary-select (A, B, and C)
inputs and the three enable (G1, G2A, and G2B)
NC 鈥?No internal connection
inputs select one of eight output lines. Two
active-low and one active-high enable inputs
reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without
external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input
for demultiplexing applications.
The SN54ALS138A and SN54AS138 are characterized for operation over the full military temperature range
of 鈥?55掳C to 125掳C. The SN74ALS138A and SN74AS138 are characterized for operation from 0掳C to 70掳C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
Y7
GND
NC
Y6
Y5
1

SN74ALS138ADRG4 产品属性

  • 2,500

  • 集成电路 (IC)

  • 逻辑 - 信号开关，多路复用器，解码器

  • 74ALS

  • 解码器/多路分解器

  • 1 x 3:8

  • 1

  • 400µA, 8mA

  • 单电源

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面贴装

  • 16-SOIC（0.154"，3.90mm 宽）

  • 16-SOIC N

  • 带卷 (TR)

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  • SN7404
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  • SN7405
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  • SN7406
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  • SN7407
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    HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUT...
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    SN7407
  • SN7407
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  • SN7408
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    QUADRUPLE 2-INPUT POSITIVE-AND GATES
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    SN7408
  • SN7408
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    QUADRUPLE 2-INPUT POSITIVE-AND GATES
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  • SN7409
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  • SN7409
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