鈥?/div>
High Capacitive-Drive Capability
鈥睞LS832A
Has Typical Delay Time of 4.8 ns
(C
L
= 50 pF) and Typical Power Dissipation
of 4.5 mW Per Gate
鈥睞S832B
Has Typical Delay Time of 3.2 ns
(C
L
= 50 pF) and Typical Power Dissipation
of Less Than 13 mW Per Gate
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
SN54ALS832A, SN54AS832B . . . J PACKAGE
SN74ALS832A, SN74AS832B . . . DW OR N PACKAGE
(TOP VIEW)
description
These devices contain six independent 2-input
OR drivers. They perform the Boolean functions
Y = A + B or Y = A
鈥?/div>
B in positive logic.
The SN54ALS832A and SN54AS832B are
characterized for operation over the full military
temperature range of 鈥?55掳C to 125掳C. The
SN74ALS832A
and
SN74AS832B
are
characterized for operation from 0掳C to 70掳C.
FUNCTION TABLE
(each driver)
INPUTS
A
H
X
L
B
X
H
L
OUTPUT
Y
H
H
L
1A
1B
1Y
2A
2B
2Y
3A
3B
3Y
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
6B
6A
6Y
5B
5A
5Y
4B
4A
4Y
SN54ALS832A, SN54AS832B . . . FK PACKAGE
(TOP VIEW)
1Y
1B
1A
V
CC
2A
2B
2Y
3A
3B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
6B
6A
6Y
5B
5A
5Y
logic symbol
鈥?/div>
1A
1B
2A
2B
3A
3B
4A
4B
5A
5B
6A
6B
1
2
4
5
7
8
12
13
15
16
18
19
17
6Y
14
5Y
11
4Y
9
3Y
鈮?
3
1Y
logic diagram (positive logic)
1A
1B
6
2Y
2A
2B
3A
3B
4A
4B
5A
5B
6A
6B
1
2
4
5
7
8
12
13
15
16
18
19
17
14
11
9
3
1Y
3Y
GND
4Y
4A
4B
6
2Y
3Y
4Y
5Y
6Y
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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