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STM32F101x6 Datasheet

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  • STM32F101xB_STMicroelectronics.pdf

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STM32F101x6
STM32F101x8 STM32F101xB
Access line, advanced ARM-based 32-bit MCU with Flash memory,
six 16-bit timers, ADC and seven communication interfaces
Preliminary Data
Features
鈻?/div>
Core: ARM 32-bit Cortex鈩?M3 CPU
鈥?36 MHz, 45 DMIPS with 1.25 DMIPS/MHz
鈥?Single-cycle multiplication and hardware
division
鈥?Nested interrupt controller with 43
maskable interrupt channels
鈥?Interrupt processing (down to 6 CPU
cycles) with tail chaining
Memories
鈥?32-to-128 Kbytes of Flash memory
鈥?6-to-16 Kbytes of SRAM
Clock, reset and supply management
鈥?2.0 to 3.6 V application supply and I/Os
鈥?POR, PDR and programmable voltage
detector (PVD)
鈥?4-to-16 MHz high-speed quartz oscillator
鈥?Internal 8 MHz factory-trimmed RC
鈥?Internal 32 kHz RC
鈥?PLL for CPU clock
鈥?Dedicated 32 kHz oscillator for RTC with
calibration
Low power
鈥?Sleep, Stop and Standby modes
鈥?V
BAT
supply for RTC and backup registers
Debug mode
鈥?Serial wire debug (SWD) and JTAG
interfaces
DMA
鈥?7-channel DMA controller
鈥?Peripherals supported: timers, ADC, SPIs,
I
2
Cs and USARTs
12-bit, 1 碌s A/D converter (16-channel)
鈥?Conversion range: 0 to 3.6 V
LQFP48
7 x 7 mm
LQFP64
10 x 10 mm
LQFP100
14 x 14 mm
鈥?Temperature sensor
鈻?/div>
鈻?/div>
Up to 80 fast I/O ports
鈥?32/49/80 5 V-tolerant I/Os
鈥?All mappable on 16 external interrupt
vectors
鈥?Atomic read/modify/write operations
Up to 6 timers
鈥?Up to three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
鈥?2 x 16-bit watchdog timers (Independent
and Window)
鈥?SysTick timer: 24-bit downcounter
Up to 7 communication interfaces
鈥?Up to 2 x I
2
C interfaces (SMBus/PMBus)
鈥?Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
鈥?Up to 2 SPIs (18 Mbit/s)
Device summary
Root part number
STM32F101C6, STM32F101R6
STM32F101C8, STM32F101R8
STM32F101V8
STM32F101RB, STM32F101VB
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Table 1.
Reference
STM32F101x6
STM32F101x8
STM32F101xB
鈻?/div>
鈻?/div>
鈻?/div>
July 2007
Rev 2
1/64
www.st.com
1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

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