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TLV2352MFKB Datasheet

  • TLV2352MFKB

  • LinCMOSE DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS

  • 310.56KB

  • 21页

  • TI

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TLV2352, TLV2352Y
LinCMOS鈩?DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B 鈥?MAY 1992 鈥?REVISED MARCH 1999
D
D
D
D
D
Wide Range of Supply Voltages
2 V to 8 V
Fully Characterized at 3 V and 5 V
Very-Low Supply-Current Drain
120
碌A
Typ at 3 V
Output Compatible With TTL, MOS, and
CMOS
Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step
D
D
D
D
High Input Impedance . . . 10
12
鈩?/div>
Typ
Extremely Low Input Bias Current
5 pA Typ
Common-Mode Input Voltage Range
Includes Ground
Built-In ESD Protection
description
The TLV2352 consists of two independent,
low-power comparators specifically designed for
single power-supply applications and operates
with power-supply rails as low as 2 V. When
powered from a 3-V supply, the typical supply
current is only 120
碌A.
symbol (each comparator)
IN +
OUT
IN 鈥?/div>
The TLV2352 is designed using the Texas Instruments LinCMOS鈩?technology and therefore features an
extremely high input impedance (typically greater than 10
12
鈩?,
which allows direct interfacing with
high-impedance sources. The outputs are N-channel open-drain configurations that require an external pullup
resistor to provide a positive output voltage swing, and they can be connected to achieve positive-logic
wired-AND relationships. The TLV2352I is fully characterized at 3 V and 5 V for operation from 鈥?40掳C to 85掳C.
The TLV2352M is fully characterized at 3 V and 5 V for operation from 鈥?55掳C to 125掳C.
The TLV2352 has internal electrostatic-discharge (ESD)-protection circuits and has been classified with a
1000-V ESD rating using Human Body Model testing. However, care should be exercised in handling this device
as exposure to ESD may result in degradation of the device parametric performance.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIO max
at 25掳C
SMALL
OUTLINE
(D)鈥?/div>
TLV2352ID
鈥?/div>
CHIP
CARRIER
(FK)
鈥?/div>
TLV2352MFK
CERAMIC
DIP
(JG)
鈥?/div>
TLV2352MJG
PLASTIC
DIP
(P)
TLV2352IP
鈥?/div>
TSSOP
(PW)鈥?/div>
TLV2352IPWLE
鈥?/div>
PLASTIC
DIP
(U)
鈥?/div>
TLV2352Y
5 mV
TLV2352MU
CHIP
FORM
(Y)
鈥?40掳C to
85掳C
鈥?55掳C to
125掳C
5 mV
鈥?The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLV2352IDR).
鈥?The PW packages are only available left-ended taped and reeled (e.g., TLV2352IPWLE)
These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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