UT1553B RTI Remote Terminal Interface
F
EATURES
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Complete MIL-STD-1553B Remote Terminal
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interface compliance
Dual-redundant data bus operation supported
Internal illegalization of selected mode code
commands
External illegal command de铿乶ition capability
Automatic DMA control and address generation
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Operational status available via dedicated lines or
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internal status register
ASD/ENASC (formerly SEAFAC) tested and
approved
Available in ceramic 84-lead leadless chip carrier and
84-pin pingrid array
Full military operating temperature range, -55掳C to
+125掳C, screened to the speci铿乧 test methods listed in
Table I of MIL-STD-883, Method 5004, Class B
JAN-quali铿乪d devices available
MODE CODE/
SUB ADDRESS
MIL-STD-1553B SERIAL BUS TRANSCEIVER I/O
IN
DECODER
CHANNEL
A
ILLEGAL
COMMAND
HOST
SYSTEM
ADDRESS
INPUTS
MEMORY
ADDRESS
CONTROL
OUTPUT MULTIPLEXING AND
SELF TEST WRAP-AROUND LOGIC
A
OUT
OUTPUT EN
COMMAND
RECOGNITION
LOGIC
MEMORY
ADDRESS
OUTPUTS
DECODER
CHANNEL
B
CONTROL
AND
ERROR LOGIC
CONTROL
INPUTS
CONTROL
OUTPUTS
TIMEOUT
MUX
DATA
TRANSFER
LOGIC
CLOCK AND
RESET LOGIC
12MHz
TIMERON
IN
B
ENCODER
OUT
RESET
16
2MHz
DATA I/O BUS
Figure 1. UT1553B RTI Functional Block Diagram
RTI-1