W162
Spread Aware鈩? Zero Delay Buffer
Features
鈥?Spread Aware鈩⑩€攄esigned to work with SSFTG
reference signals
鈥?Two banks of four outputs, plus the fed back output
鈥?Outputs may be three-stated
鈥?Available in 16-pin SOIC or SSOP package
鈥?Extra strength output drive available (-19 version)
鈥?Internal feedback
Table 1. Input Logic
SEL1
0
0
1
1
SEL0
0
1
0
1
QA0:3
Three-
State
Active
Active
Active
QB0:3
Three-
State
Three-
State
Active
Active
PLL
Shutdown
Active,
Utilized
Shutdown,
Bypassed
Active,
Utilized
QFB
Active
Active
Active
Active
Key Specifications
Operating Voltage: ............................................... 3.3V卤10%
Operating Range: .................................15 < f
OUT
< 133 MHz
Cycle-to-Cycle Jitter: .................................................. 250 ps
Output to Output Skew: .............................................. 150 ps
Propagation Delay: ..................................................... 150 ps
Block Diagram
Pin Configuration
QFB
REF
PLL
REF
MUX
QA0
QA1
QA2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QFB
QA3
QA2
VDD
GND
QB3
QB2
SEL0
QA0
QA1
VDD
GND
QB0
QA3
QB0
SEL0
QB1
SEL1
SEL1
QB1
QB2
QB3
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?408-943-2600
July 31, 2000, rev. *B
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