庐
XC4000E
Logic Cell Array Family
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Features
鈥?Third Generation Field-Programmable Gate Arrays
鈥?On-chip ultra-fast RAM with synchronous write option
鈥?Dual-port RAM option
鈥?Fully PCI compliant
鈥?Abundant flip-flops
鈥?Flexible function generators
鈥?Dedicated high-speed carry-propagation circuit
鈥?Wide edge decoders (four per edge)
鈥?Hierarchy of interconnect lines
鈥?Internal 3-state bus capability
鈥?8 global low-skew clock or signal distribution network
鈥?Flexible Array Architecture
鈥?Programmable logic blocks and I/O blocks
鈥?Programmable interconnects and wide decoders
鈥?Sub-micron CMOS Process
鈥?High-speed logic and Interconnect
鈥?Low power consumption
鈥?Systems-Oriented Features
鈥?IEEE 1149.1-compatible boundary-scan logic support
鈥?Programmable output slew rate (2 modes)
鈥?Programmable input pull-up or pull-down resistors
鈥?12-mA sink current per output
鈥?24-mA sink current per output pair
鈥?Configured by Loading Binary File
鈥?Unlimited reprogrammability
鈥?Six programming modes
鈥?XACT Development System runs on 鈥?86/鈥?86/
Pentium-type PC, Apollo, Sun-4, and Hewlett-Packard
700 series
鈥?Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
鈥?Fully automatic partitioning, placement and routing
鈥?Interactive design editor for design optimization
鈥?288 macros, 34 hard macros, RAM/ROM compiler
Description
The XC4000E family of Field-Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI,
while avoiding the initial cost, time delay, and inherent risk
of a conventional masked gate array.
The XC4000E family provides a regular, flexible, pro-
grammable architecture of Configurable Logic Blocks
(CLBs), interconnected by a powerful hierarchy of versa-
tile routing resources, and surrounded by a perimeter of
programmable Input/Output Blocks (IOBs).
XC4000E devices have generous routing resources to
accommodate the most complex interconnect patterns.
They are customized by loading configuration data into
the internal memory cells. The FPGA can either actively
read its configuration data out of external serial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA (slave and peripheral
modes).
The XC4000E family is supported by powerful and sophis-
ticated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block place-
ment and routing of interconnects, and finally the creation
of the configuration bit stream.
FPGAs are ideal for shortening the design and develop-
ment cycle, but they also offer a cost-effective solution for
production rates well beyond 1,000 systems per month.
The XC4000E family is a superset of the popular XC4000
family. For a detailed description of the device architec-
ture, configuration methods, pin functionality, package
pin-outs and dimensions, see the Xilinx Programmable
Logic Data Book.
The following pages describes the new features of the
XC4000E family and list electrical and timing parameters.
Table 1. The XC4000E Family of Field-Programmable Gate Arrays
Device
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
Number of IOBs
XC4003E
3,000
10 x 10
100
360
30
3,200
80
XC4005E
5,000
14 x 14
196
616
42
6,272
112
XC4006E
6,000
16 x 16
256
768
48
8,192
128
XC4008E
8,000
18 x 18
324
936
54
10,368
144
XC4010E
10,000
20 x 20
400
1,120
60
12,800
160
XC4013E
13,000
24 x 24
576
1,536
72
18,432
192
XC4020E XC4025E
20,000
28 x 28
784
2,016
84
25,088
224
25,000
32 x 32
1,024
2,560
96
32,768
256
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