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ILOG
S
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OMMUNICATION
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ONTROLLER
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RODUCT
B
RIEF
Z85C30
CMOS SCC S
ERIAL
C
OMMUNICATION
C
ONTROLLER
FEATURES
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Low Power CMOS
Two Independent, 0 to 4.0 Mbit/sec, Full-Duplex
Channels, each with a Separate Crystal Oscillator,
Baud Rate Generator, and Digital Phase-Locked Loop
for Clock Recovery.
Multi-Protocol Operation under Program Control;
Programmable for NRZ, NRZI, or FM Data Encoding.
Asynchronous Mode with Five to Eight Bits and One,
One and One-Half, or Two Stop Bits Per Character;
Programmable Clock Factor; Break Detection and
Generation; Parity, Overrun, and Framing Error
Detection.
Supports T1 Digital Trunk
Clock Speeds: 8, 10 and 16 MHz
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New programmable WR' (write register 7 prime) to
enable new features
Improvements to support SDLC mode of synchronous
communication:
- Improve functionality to ease sending back-to-back
frames
- Automatic SDLC opening Flag transmission*
- Automatic Tx Underrun/EOM Latch reset in SDLC
mode*
- Automatic /RTS deactivation*
- TxD pin forced "H" in SDLC NRZI mode after closing
flag*
- Complete CRC reception*
- Improved response to Abort sequence in status FIFO
- Automatic Tx CRC generator preset/reset
- Extended read for write registers*
- Write data set-up timing improvement
Improved AC Timing
- Three to 3.6 PCLK access recovery time
- Programmable /DTR//REQ timing*
- Write data to falling edge of /WR set-up time
requirement is now eliminated
- Reduced /INT timing
Other features include:
- Extended read function to read back the written
value to the write registers*
- Latching RR0 during read
- RR0, bit D7 and RR 10, bit D6 now has reset default
value.
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Synchronous Mode with Internal or External Character
Synchronization on One or Two Synchronous
Characters and CRC Generation and Checking with
CRC-16 or CRC-CCITT Preset to Either 1s or 0s.
SDLC/HDLC Mode with Comprehensive Frame-Level
Control, Automatic Zero Insertion and Deletion, I-Field
Residue Handling, Abort Generation and Detection,
CRC Generation and Checking, SDLC Loop Mode
Operation.
Local Loopback and Auto Echo Modes
Enhanced DMA Support:
- 10 x 19-Bit Status FIFO
- 14-Bit Byte Counter
Available in 40-Pin PDIP and 44-Pin PLCC Packages.
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Some of the features listed above are available by default,
and some of them (features with "*") are disabled on default
to maintain compatibility with the existing SCC design, and
"program to enable" through WR7'.
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