40/48-Pin PDIP and 44-Pin PLCC Packages鈥?/div>
+4.5 I V,, I +5.5-Volt Operating Range
Low-Power CMOS
0掳C to +70掳C Temperature Range
GENERAL DESCRIPTION
The Z16COl/CO2 CPU are members of the 16-bit
processor and controller family. Designed using a
RISC-like Load/Store architecture, the CPU can operate in
either system or normal modes, permitting privileged
operations and improving operating system organization
and implementation.
To boost the main CPU鈥?performance capability, the
s
processor core includes hardwired control and is a
16-bit real-time processor functioning at register access
speeds. Register flexibility is created by grouping or
overlapping multiple registers, and by allowing extended
register file capabilities as the system expands. Easy
extended register file control is accomplished through a
single instruction stream communication.
TheCPUsupportsthreetypesof interrupts (non-maskable,
vectored, and non-vectored) and four traps (system call,
extended process architecture instruction, privileged
instructions, and segmentation trap). The vectored and
non-vectored interrupts are maskable.
The processor鈥?resources include seven data types that
s
range from bits to 32-bit long words, and byte and word
strings, plus eight user-selectable addressing modes. The
nine basic instruction types can be combined with various
data types and addressing modes to form a powerful set
of 414 instructions.
The extended processing architecture features provide a
modular approach to expanding both the hardware and
software capabilities of the Z16COl/CO2.
Notes:
All Signals with a preceding front slash, 鈥?鈥? are active Low, e.g.:
B/AN(WORDis active Low);
/B/W^(BYTE
is active Low, only).
Powerconnections follow conventionaldescriptions below:
Connection
Power
Ground
Circuit
鈥渃c
GND
Device
V DO
鈥渟s
cPs95scc0103
(3/95)
1