PIC16F818/819
2.2.2.1
Status Register
The Status register, shown in Register 2-1, contains the
arithmetic status of the ALU, the Reset status and the
bank select bits for data memory.
The Status register can be the destination for any
instruction, as with any other register. If the Status reg-
ister is the destination for an instruction that affects the
Z, DC or C bits, then the write to these three bits is dis-
abled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
For example,
CLRF STATUS,
will clear the upper three
bits and set the Z bit. This leaves the Status register as
鈥?00u
u1uu鈥?/div>
(where
u
= unchanged).
It is recommended, therefore, that only
BCF, BSF,
SWAPF
and
MOVWF
instructions are used to alter the
Status register because these instructions do not affect
the Z, C or DC bits from the Status register. For other
instructions not affecting any status bits, see
Section 13.0 鈥淚nstruction Set Summary鈥?
Note:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the
SUBLW
and
SUBWF
instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
IRP
bit 7
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 0
bit 7
IRP:
Register Bank Select bit (used for indirect addressing)
1
= Bank 2, 3 (100h-1FFh)
0
= Bank 0, 1 (00h-FFh)
RP<1:0>:
Register Bank Select bits (used for direct addressing)
11
= Bank 3 (180h-1FFh)
10
= Bank 2 (100h-17Fh)
01
= Bank 1 (80h-FFh)
00
= Bank 0 (00h-7Fh)
Each bank is 128 bytes.
TO:
Time-out bit
1
= After power-up,
CLRWDT
instruction or
SLEEP
instruction
0
= A WDT time-out occurred
PD:
Power-down bit
1
= After power-up or by the
CLRWDT
instruction
0
= By execution of the
SLEEP
instruction
Z:
Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
DC:
Digit carry/borrow bit (ADDWF,
ADDLW, SUBLW
and
SUBWF
instructions)
(1)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
C:
Carry/borrow bit (ADDWF,
ADDLW, SUBLW
and
SUBWF
instructions)
(1,2)
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result occurred
Note 1:
For borrow, the polarity is reversed. A subtraction is executed by adding the two鈥檚
complement of the second operand.
2:
For rotate (RRF,
RLF)
instructions, this bit is loaded with either the high or low order
bit of the source register.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
鈥?鈥?= Bit is set
U = Unimplemented bit, read as 鈥?鈥?/div>
鈥?鈥?= Bit is cleared
x = Bit is unknown
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39598D-page 16
Preliminary
铮?/div>
2003 Microchip Technology Inc.
prev
next