CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Switching Waveforms
(continued)
NOP,STALL and DESELECT Cycles
[24, 25, 27]
1
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A1
2
3
4
5
6
7
8
9
10
A2
A3
A4
A5
t
CHZ
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON鈥橳 CARE
UNDEFINED
ZZ Mode Timing
[28, 29]
CLK
t ZZ
t
ZZREC
ZZ
t
ZZI
I
SUPPLY
I DDZZ
t RZZI
DESELECT or READ Only
ALL INPUTS
(except ZZ)
Outputs (Q)
High-Z
DON鈥橳 CARE
Notes:
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05353 Rev. *D
Page 21 of 27
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