CY7C1461AV33 Datasheet

IC型号：
CY7C1461AV33
PDF描述：
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with ...
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1385.20KB
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0页
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CYPRESS

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CY7C1461AV33

CY7C1463AV33

CY7C1465AV33

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to the address bus

is loaded into the Address Register. The write signals are

latched into the Control Logic block. The data lines are

automatically tri-stated regardless of the state of the OE input

signal. This allows the external logic to present the data on

DQs and DQP

On the next clock rise the data presented to DQs and DQP

(or a subset for byte write operations, see truth table for

details) inputs is latched into the device and the write is

complete. Additional accesses (Read/Write/Deselect) can be

initiated on this cycle.

The data written during the Write operation is controlled by

signals. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33

provides byte write capability that is described in the truth

table. Asserting the Write Enable input (WE) with the selected

Byte Write Select input selectively writes to only the desired

bytes. Bytes not selected during a byte write operation

remains unaltered. A synchronous self timed write mechanism

has been provided to simplify the write operations. Byte write

capability has been included to greatly simplify

Read/Modify/Write sequences, which can be reduced to

simple byte write operations.

Because the CY7C1461AV33/CY7C1463AV33/CY7C1465AV33

is a common IO device, data must not be driven into the device

while the outputs are active. The Output Enable (OE) can be

deasserted HIGH before presenting data to the DQs and

DQP

inputs. Doing so tri-states the output drivers. As a safety

precaution, DQs and DQP

are automatically tri-stated during

the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has

an on-chip burst counter that allows the user the ability to

supply a single address and conduct up to four Write opera-

tions without reasserting the address inputs. ADV/LD must be

driven LOW to load the initial address, as described in the

Single Write Access section above. When ADV/LD is driven

HIGH on the subsequent clock rise, the Chip Enables (CE

, and CE

) and WE inputs are ignored and the burst

counter is incremented. The correct BW

inputs must be

driven in each cycle of the burst write, to write the correct bytes

of data.

Interleaved Burst Address Table

(MODE = Floating or V

)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation 鈥渟leep鈥?mode. Two

clock cycles are required to enter into or exit from this 鈥渟leep鈥?/div>

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the 鈥渟leep鈥?mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the 鈥渟leep鈥?mode. CE

, CE

, and CE

, must remain inactive

for the duration of t

ZZREC

after the ZZ input returns LOW.

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

ZZ Mode Electrical Characteristics

Parameter

DDZZ

ZZS

ZZREC

ZZI

RZZI

Description

Sleep mode standby current

Device operation to ZZ

ZZ recovery time

ZZ active to sleep current

ZZ Inactive to exit sleep current

Test Conditions

ZZ > V

鈥?0.2V

ZZ > V

鈥?0.2V

ZZ < 0.2V

This parameter is sampled

CYC

Min

Max

100

CYC

Unit

Document #: 38-05356 Rev. *F

Page 10 of 31

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