ADSP-2185L
TIMING PARAMETERS
(See page 15, Frequency Depending for Timing Specifications, for timing definitions.)
Parameter
Clock Signals and Reset
Timing Requirements:
CLKIN External Clock Period
t
CKI
t
CKIL
CLKIN Width Low
t
CKIH
CLKIN Width High
Switching Characteristics:
CLKOUT Width Low
t
CKL
t
CKH
CLKOUT Width High
CLKIN High to CLKOUT High
t
CKOH
Control Signals
Timing Requirement:
RESET
Width Low
t
RSP
t
MS
Mode Setup before
RESET
High
t
MH
Mode Hold after
RESET
High
5t
CK1
2
5
ns
ns
ns
38
15
15
0.5t
CK
鈥?7
0.5t
CK
鈥?7
0
100
ns
ns
ns
ns
ns
ns
Min
Max
Unit
20
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
t
CKI
t
CKIH
CLKIN
t
CKIL
t
CKOH
t
CKH
CLKOUT
t
CKL
PF(3:0)
*
t
MS
RESET
t
MH
*
PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 19. Clock Signals
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