ADSP-2185L
Parameter
Serial Ports
Timing Requirements:
SCLK Period
t
SCK
DR/TFS/RFS Setup before SCLK Low
t
SCS
t
SCH
DR/TFS/RFS Hold after SCLK Low
t
SCP
SCLK
IN
Width
Switching Characteristics:
CLKOUT High to SCLK
OUT
t
CC
t
SCDE
SCLK High to DT Enable
SCLK High to DT Valid
t
SCDV
t
RH
TFS/RFS
OUT
Hold after SCLK High
t
RD
TFS/RFS
OUT
Delay from SCLK High
DT Hold after SCLK High
t
SCDH
t
TDE
TFS (Alt) to DT Enable
t
TDV
TFS (Alt) to DT Valid
SCLK High to DT Disable
t
SCDD
t
RDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
Min
Max
Unit
50
4
8
15
0.25t
CK
0
0
15
0
0
14
15
15
0.25t
CK
+ 10
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CC
t
CC
t
SCP
t
SCS
t
SCH
t
SCK
SCLK
t
SCP
DR
TFS
IN
RFS
IN
t
RD
t
RH
RFS
OUT
TFS
OUT
t
SCDV
t
SCDE
DT
t
SCDD
t
SCDH
t
TDE
t
TDV
TFS
OUT
ALTERNATE
FRAME MODE
t
RDV
RFS
OUT
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
t
TDE
t
TDV
TFS
IN
ALTERNATE
FRAME MODE
t
RDV
RFS
IN
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 24. Serial Ports
REV. A
鈥?3鈥?/div>
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