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AD8318

Table 4. Input Impedance for Select Frequency

Frequency

MHz

100

456

900

1900

2200

3600

5300

5800

8000

S11

Real

0.918

0.905

0.834

0.605

0.524

0.070

鈭?.369

鈭?.326

鈭?.390

Imaginary

鈭?.041

鈭?.183

鈭?.350

鈭?.595

鈭?.616

鈭?.601

鈭?.305

鈭?.286

鈭?.062

VSET

I

SET

Impedance 鈩?/div>

(Series)

04853-026

927-j491

173-j430

61-j233

28-j117

28-j102

26-j49

20-j16

22-j16

22-j3

3.13k鈩?/div>

CMOP

Figure 26. VSET Interface

The slope is given by 鈥揑

D

脳 X 脳 3.13 k鈩?= 鈥?00 mV 脳 X. For

example, if a resistor divider to ground is used to generate a

V

SET

voltage of V

OUT

/2, then X = 2. The slope will be set to

鈥? V/decade or 鈥?0 mV/dB.

TEMPERATURE COMPENSATION OF OUTPUT

VOLTAGE

The AD8318 functionality includes the capability to

externally trim the temperature drift. Attaching a ground-

referenced resistor to the T

ADJ

pin alters an internal current,

which works to minimize intercept drift vs. temperature. As

a result, the T

ADJ

resistor can be optimized for operation at

different frequencies.

I

COMP

2V

OUTPUT INTERFACE

The VOUT pin is driven by a PNP output stage. An internal 10 鈩?/div>

resistor is placed in series with the emitter follower output and

the VOUT pin. The rise time of the output is limited mainly by

the slew on CLPF. The fall time is an RC limited slew given by

the load capacitance and the pull-down resistance at VOUT.

There is an internal pull-down resistor of 350 鈩? Any resistive

load at VOUT is placed in parallel with the internal pull-down

resistor and provides additional discharge current.

VPSO

CLPF

10鈩?/div>

+

0.2V

鈥?/div>

VOUT

V

INTERNAL

~0.4V

2k鈩?/div>

TADJ

04853-027

Figure 27. TADJ Interface

150鈩?/div>

200鈩?/div>

04853-025

CMOP

Figure 25. Output Interface

A resistor, nominally 500

鈩?/div>

for optimal temperature

compensation at 2.2 GHz input frequency, is connected

between this pin and ground (see Figure 22). The value of

this resistor partially determines the magnitude of an analog

correction coefficient, which is employed to reduce

intercept drift.

Table 5 lists recommended resistors for other frequencies.

These resistors have been chosen to provide the best overall

temperature drift based on measurements of a diverse

population of devices.

The relationship between output temperature drift and

frequency is not linear and cannot be easily modeled. As a

result, experimentation is required to choose the correct

T

ADJ

resistor at frequencies not listed in Table 5.

SETPOINT INTERFACE

The V

SET

input drives the high impedance (250 k鈩? input of an

internal op amp. The V

SET

voltage appears across the internal

3.13 k鈩?resistor to generate I

SET

. When a portion of V

OUT

is

applied to VSET, the feedback loop forces 鈭扞

D

脳 log

10

(V

IN

/V

INTERCEPT

) = I

SET

. If V

SET

= V

OUT

/X, then I

SET

=

V

OUT

/(X 脳 3.13 k鈩?. The result is

V

OUT

= (鈭扞

D

脳 3.13 k鈩?脳 X) 脳 log

10

(V

IN

/V

INTERCEPT

)

Rev. 0 | Page 13 of 24

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