鈥淗鈥?/div>
I/O port
I/O port
Address bus
/data bus
Address bus
/data bus
A
8
/D
7
I/O port
I/O port
Data bus width
BYTE pin level
P0
0
to P0
7
P1
0
to P1
7
P2
0
P2
1
to P2
7
P3
0
P3
1
to P3
7
P4
0
to P4
3
Port P4
0
to P4
3
function select bit = 1
P4
0
to P4
3
Port P4
0
to P4
3
function select bit = 0
P4
4
to P4
7
P5
0
to P5
3
P5
4
P5
5
P5
6
P5
7
Address bus
Address bus
/data bus
(Note 2)
Address bus
/data bus
(Note 2)
Address bus
Address bus
/data bus
(Note 2)
Address bus
/data bus
(Note 2)
Address bus
I/O port
Address bus
I/O port
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
CS (chip select) or programmable I/O port
(For details, refer to 鈥淏us control鈥?
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to 鈥淏us control鈥?
HLDA
HOLD
ALE
RDY
HLDA
HOLD
ALE
RDY
HLDA
HOLD
ALE
RDY
HLDA
HOLD
ALE
RDY
HLDA
HOLD
ALE
RDY
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Note 2: Address bus when in separate bus mode.
26