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M30620FCAFP Datasheet

  • M30620FCAFP

  • M16C/62(M16C/62A .M16C/62M) Group USER＇S MANUAL

  • 8927.88KB

  • Mitsubishi   Mitsubishi

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Mitsubishi microcomputers
M16C / 62A Group
Clock Generating Circuit
Figure 1.10.4 shows the system clock control registers 0 and 1.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Bit symbol
CM00
CM01
CM02
CM03
CM04
CM05
CM06
CM07
Address
0006
16
Bit name
Clock output function
select bit
(Valid only in single-chip
mode)
WAIT peripheral function
clock stop bit
When reset
48
16
Function
b1 b0
RW
0 0 : I/O port P5
7
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN
-X
COUT
drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
Port X
C
select bit
Main clock (X
IN
-X
OUT
)
stop bit (Note 3, 4, 5)
Main clock division select
bit 0 (Note 7)
System clock select bit
(Note 6)
0 : I/O port
1 : X
CIN
-X
COUT
generation
0 : On
1 : Off
0 : CM16 and CM17 valid
1 : Division by 8 mode
0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A
16
) to 鈥?鈥?before writing to this register.
Note 2: Changes to 鈥?鈥?when shiffing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with X
IN
, set this bit to 鈥?鈥? When main clock oscillation is operating by itself, set system clock select
bit (CM07) to 鈥?鈥?before setting this bit to 鈥?鈥?
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to 鈥?鈥? X
OUT
turns 鈥淗鈥? The built-in feedback resistor remains being connected, so X
IN
turns
pulled up to X
OUT
(鈥淗鈥? via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to 鈥?鈥?and stabilize the sub-clock oscillating before setting to this bit from 鈥?鈥?to 鈥?鈥?
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to 鈥?鈥?and stabilize the
main clock oscillating before setting this bit from 鈥?鈥?to 鈥?鈥?
Note 7: This bit changes to 鈥?鈥?when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: f
C32
is not included.
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
0
0
Symbol
CM1
Bit symbol
CM10
Address
0007
16
Bit name
All clock stop control bit
(Note4)
When reset
20
16
Function
0 : Clock on
1 : All clocks off (stop mode)
Always set to
鈥?鈥?/div>
Always set to
鈥?鈥?/div>
Always set to
鈥?鈥?/div>
Always set to
鈥?鈥?/div>
0 : LOW
1 : HIGH
b7 b6
RW
Reserved bit
Reserved bit
Reserved bit
Reserved bit
CM15
CM16
CM17
X
IN
-X
OUT
drive capacity
select bit (Note 2)
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A
16
) to 鈥?鈥?before writing to this register.
Note 2: This bit changes to 鈥?鈥?when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006
16
) is 鈥?鈥? If 鈥?鈥? division mode is
fixed at 8.
Note 4: If this bit is set to 鈥?鈥? X
OUT
turns 鈥淗鈥? and the built-in feedback resistor is cut off. X
CIN
and X
COUT
turn high-
impedance state.
Figure 1.10.4. Clock control registers 0 and 1
37

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