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M30620FCAFP Datasheet

  • M30620FCAFP

  • M16C/62(M16C/62A .M16C/62M) Group USER＇S MANUAL

  • 8927.88KB

  • Mitsubishi   Mitsubishi

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Mitsubishi microcomputers
M16C / 62A Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA1 request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM1SL
Address
03BA
16
When reset
00
16
Bit symbol
Bit name
DMA request cause
select bit
b3 b2 b1 b0
Function
0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3(DMS=0)
/serial I/O3 (DMS=1)
0 1 1 0 : Timer A4 (DMS=0)
/serial I/O4 (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
/two edges of INT1 (DMS=1)
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive
R
W
DSEL0
DSEL1
DSEL2
DSEL3
Nothing is assigned.
In an attempt to write to these bits, write 鈥?鈥? The value, if read, turns out to be 鈥?鈥?
DMS
DSR
DMA request cause
expansion bit
Software DMA
request bit
0 : Normal
1 : Expanded cause
If software trigger is selected, a
DMA request is generated by
setting this bit to 鈥?鈥?(When read,
the value of this bit is always 鈥?鈥?
DMAi control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMiCON(i=0,1)
Address
002C
16
, 003C
16
When reset
00000X00
2
Bit symbol
DMBIT
DMASL
DMAS
DMAE
DSD
DAD
Bit name
Transfer unit bit select bit
Repeat transfer mode
select bit
DMA request bit (Note 1)
DMA enable bit
Source address direction
select bit (Note 3)
0 : 16 bits
1 : 8 bits
Function
R
W
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
(Note 2)
Destination address
0 : Fixed
direction select bit (Note 3) 1 : Forward
Nothing is assigned.
In an attempt to write to these bits, write 鈥?鈥? The value, if read, turns out to be 鈥?鈥?
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to 鈥?鈥?
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to 鈥?鈥?simultaneously.
Figure 1.13.3. DMAC register (2)
69

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