Mitsubishi microcomputers
M16C / 62A Group
Timer A
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.14.3 shows the block diagram of timer A. Figures 1.14.4 to 1.14.6 show the timer A-related
registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
鈥?Timer mode: The timer counts an internal count source.
鈥?Event counter mode: The timer counts pulses from an external source or a timer over flow.
鈥?One-shot timer mode: The timer stops counting when the count reaches 鈥?000
16
鈥?
鈥?Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
f
1
f
8
f
32
f
C32
Polarity
selection
TAi
IN
(i = 0 to 4)
鈥?Timer
鈥?One shot
鈥?PWM
鈥?Timer
(gate function)
鈥?Event counter
Data bus low-order bits
Low-order
8 bits
Reload register (16)
High-order
8 bits
Counter (16)
Clock selection
Up count/down count
Always down count except
in event counter mode
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Addresses
0387
16
0386
16
0389
16
0388
16
038B
16
038A
16
038D
16
038C
16
038F
16
038E
16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
Count start flag
(Address 0380
16
)
Down count
External
trigger
TB2 overflow
TAj overflow
(j = i 鈥?1. Note, however, that j = 4 when i = 0)
Up/down flag
(Address 0384
16
)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
TAi
OUT
(i = 0 to 4)
Pulse output
Toggle flip-flop
Figure 1.14.3. Block diagram of timer A
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TAiMR(i=0 to 4)
Address
When reset
0396
16
to 039A
16
00
16
Bit symbol
TMOD0
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
RW
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.14.4. Timer A-related registers (1)
78