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24AA512 Datasheet

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24AA512/24LC512/24FC512
8.0
READ OPERATION
8.2
Random Read
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to 鈥?/div>
1
鈥? There are three basic types of
read operations: current address read, random read
and sequential read.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX512 as part of a write operation (R/W bit set to
鈥?/div>
0
鈥?. After the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal address pointer is set. Then, the master issues
the control byte again but with the R/W bit set to a one.
The 24XX512 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer but does generate a Stop
condition which causes the 24XX512 to discontinue
transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
8.1
Current Address Read
The 24XX512 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by 鈥?/div>
1
鈥? Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to 鈥?/div>
1
鈥?
the 24XX512 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a Stop condition and the
24XX512 discontinues transmission (Figure 8-1).
8.3
Sequential Read
FIGURE 8-1:
S
T
A
R
T
CURRENT ADDRESS
READ
CONTROL
BYTE
DATA
BYTE
S
T
O
P
P
A
C
K
N
O
A
C
K
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S 1 0 1 0 A AA 1
2 1 0
Sequential reads are initiated in the same way as a
random read except that after the 24XX512 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX512 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide
sequential reads, the 24XX512 contains an internal
address pointer which is incremented by one at the
completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address FFFF to address
0000 if the master acknowledges the byte received
from the array address FFFF.
FIGURE 8-2:
BUS ACTIVITY
MASTER
S
T
A
R
T
RANDOM READ
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
S
T
A
R
T
CONTROL
BYTE
DATA
BYTE
S
T
O
P
P
A
C
K
N
O
A
C
K
SDA LINE
BUS ACTIVITY
S1 0 1 0 AAA0
2 1 0
A
C
K
A
C
K
A
C
K
S 1 0 1 0 A A A1
2 1 0
X = Don鈥檛 Care Bit
DS21754E-page 12
铮?/div>
2004 Microchip Technology Inc.

24AA512 PDF文件相关型号

24FC512（汉）,24LC512（汉）

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