24AA512 Datasheet

IC型号：
24AA512
文件大小：
778.61KB
PDF页数：
44页
芯片厂家：
MICROCHIP

阅览下载纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

24AA512/24LC512/24FC512

4.0

BUS CHARACTERISTICS

4.5

Acknowledge

The following

bus protocol

has been defined:

鈥?Data transfer may be initiated only when the bus

is not busy.

鈥?During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line, while the clock line is high, will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit. See Figure 4-2 for acknowledge timing.

Note:

The 24XX512 does not generate any

Acknowledge bits if an internal programming

cycle is in progress.

4.1

Bus Not Busy (A)

Both data and clock lines remain high.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

A device that acknowledges must pull down the SDA

line during the Acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24XX512) will leave the data line high to enable

the master to generate the Stop condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must end with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

DS21754E-page 6

铮?/div>

2004 Microchip Technology Inc.

prev next

24AA512 PDF文件相关型号

24FC512（汉）,24LC512（汉）

24AA512相关型号PDF文件下载

型号

版本

描述

厂商

下载
24AA00

英文版

128-Bit I2C™ Bus Serial EEPROM

24AA00
24AA00

英文版

128 Bit I 2 C? Bus Serial EEPROM

MICROCHIP ...

24AA00
24AA01

英文版

1K I2C™ Serial EEPROM

24AA01
24AA01

英文版

1K I2C Serial EEPROM

MICROCHIP ...

24AA01
24AA01

英文版

1K/2K 1.8V I 2 C O Serial EEPROMs

MICROCHIP ...

24AA01
24AA02

英文版

2K I2C™ Serial EEPROM

24AA02
24AA02

英文版

2K I2C Serial EEPROM

MICROCHIP ...

24AA02
24AA02

英文版

1K/2K 1.8V I 2 C O Serial EEPROMs

MICROCHIP ...

24AA02
24AA04

英文版

4K I2C™ Serial EEPROM

24AA04
24AA04

英文版

4K/8K 1.8V I2C Serial EEPROMs

MICROCHIP ...

24AA04
24AA08

英文版

8K I2C™ Serial EEPROM

24AA08
24AA08

英文版

24AA08
24AA08

英文版

4K/8K 1.8V I2C Serial EEPROMs

MICROCHIP ...

24AA08
24AA08

英文版

8K IC SERIAL EEPROM

MICROCHIP ...

24AA08
24AA16

英文版

16K I2C™ Serial EEPROM

24AA16
24AA16

英文版

16K 1.8V I2C SERIAL EEPROM

MICROCHIP ...

24AA16
24AA16

英文版

16K 1.8V I 2 C O Serial EEPROM

MICROCHIP ...

24AA16
24AA32

英文版

32K 1.8V I2C™ Smart Serial™ EEPROM

24AA32
24AA32

英文版

32K 1.8V I 2 C O Smart Serial EEPROM

MICROCHIP ...

24AA32
24AA52

英文版

2K 2.2V I?C? Serial EEPROM with Software Write-Protect

24AA52

24AA512 Datasheet

PDF预览

24AA512 PDF文件相关型号

24AA512相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

24AA512 Datasheet

PDF预览

24AA512 PDF文件相关型号

24AA512相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

建议反馈

PDF纠错X