PIC16C641 Datasheet

IC型号：
PIC16C641
PDF描述：
8-Bit EPROM Microcontrollers with Analog Comparators
文件大小：
661.21KB
PDF页数：
137页
芯片厂家：
MICROCHIP

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PIC16C64X & PIC16C66X

4.3

PCL and PCLATH

4.3.2

STACK

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is readable and

writable. The high byte (PC<12:8>) is not directly read-

able or writable and comes from PCLATH. On any

reset, the PC is cleared. Figure 4-11 shows the two

situations for the loading of the PC. The upper example

in the 铿乬ure shows how the PC is loaded on a write to

PCL (PCLATH<4:0>

鈫?/div>

PCH). The lower example in

the 铿乬ure shows how the PC is loaded during a

CALL

GOTO

instruction (PCLATH<4:3>

鈫?/div>

PCH).

PIC16C64X & PIC16C66X devices have an 8 level

deep x 13-bit wide hardware stack (Figure 4-2). The

stack space is not part of either program or data space

and the stack pointer is not readable or writable. The

PC is PUSHed onto the stack when a

CALL

instruction

is executed or an interrupt causes a branch. The stack

is POPed in the event of a

RETURN, RETLW

or a

RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the 铿乺st

push. The tenth push overwrites the second push (and

so on).

Note 1:

There are no status bits to indicate stack

over铿俹w or stack under铿俹w conditions.

Note 2:

There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL,

RETURN, RETLW,

and

RETFIE

instruc-

tions, or the vectoring to an interrupt

address.

FIGURE 4-11: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH

PCLATH<4:0>

PCL

Instruction with

PCL as

Destination

ALU result

PCLATH

PCH

PCLATH<4:3>

Opcode <10:0>

PCLATH

11 10

PCL

GOTO, CALL

4.4

Program Memory Paging

4.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an

offset to the program counter (ADDWF

PCL).

When

doing a table read using a computed GOTO method,

care should be exercised if the table location crosses a

PCL memory boundary (each 256 byte block). Refer to

the application note

鈥淚mplementing a Table Read鈥?/div>

(AN556).

PIC16C642 and PIC16C662 devices have 4K of pro-

gram memory, but the

CALL

and

GOTO

instructions only

have an 11-bit address range. This 11-bit address

range allows a branch within a 2K program memory

page size. To allow

CALL

and

GOTO

instructions to

address the entire 4K program memory address range,

there must be another bit to specify the program mem-

ory page. This paging bit comes from the PCLATH<3>

bit (Figure 4-11). When doing a

CALL

GOTO

instruc-

tion, the user must ensure that this page select bit

(PCLATH<3>) is programmed so that the desired pro-

gram memory page is addressed. If a return from a

CALL

instruction (or interrupt) is executed, the entire

13-bit PC is pushed onto the stack. Therefore, manipu-

lation of the PCLATH<3> bit is not required for the

return instructions (which POPs the address from the

stack).

Note:

The PIC16C64X & PIC16C66X ignore the

PCLATH<4> bit, which is used for program

memory pages 2 and 3 (1000h - 1FFFh).

The use of PCLATH<4> as a general pur-

pose read/write bit is not recommended

since this may affect upward compatibility

with future products.

漏

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 27

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