PIC16C641 Datasheet

  • PIC16C641

  • 8-Bit EPROM Microcontrollers with Analog Comparators

  • 661.21KB

  • 137页

  • MICROCHIP   MICROCHIP

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PIC16C64X & PIC16C66X
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example
1
1
NOP
No Operation
[
label
]
None
No operation
None
00
0000
0xx0
0000
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Return from Interrupt
[
label
]
None
TOS
鈫?/div>
PC,
1
鈫?/div>
GIE
None
00
0000
0000
1001
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by set-
ting Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
NOP
RETFIE
No operation.
Words:
Cycles:
Example
1
2
RETFIE
After Interrupt
PC =
GIE =
TOS
1
OPTION
Syntax:
Operands:
Operation:
Encoding:
Description:
Load Option Register
[
label
]
None
(W)
鈫?/div>
OPTION
00
0000
0110
0010
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Return with Literal in W
[
label
]
RETLW k
0
鈮?/div>
k
鈮?/div>
255
k
鈫?/div>
(W);
TOS
鈫?/div>
PC
None
11
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
OPTION
Status Affected: None
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Words:
Cycles:
Example
1
1
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
Words:
Cycles:
Example
1
2
CALL TABLE
鈥?/div>
鈥?/div>
鈥?/div>
TABLE ADDWF
RETLW
RETLW
鈥?/div>
鈥?/div>
鈥?/div>
RETLW
;W contains table
;offset value
;W now has table value
;W = offset
;Begin table
;
PC
k1
k2
kn
; End of table
Before Instruction
W
W
=
=
0x07
value of k8
After Instruction
DS30559A-page 82
1996 Microchip Technology Inc.

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