24AA01 Datasheet

IC型号：
24AA01
PDF描述：
1K I2C™ Serial EEPROM
文件大小：
791.40KB
PDF页数：
34页
芯片厂家：
Microchip

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24AA01/24LC01B

7.0

READ OPERATION

7.3

Sequential Read

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to 鈥?/div>

鈥? There are three basic types

of read operations: current address read, random read

and sequential read.

Sequential reads are initiated in the same way as a

random read, except that once the 24XX01 transmits

the first data byte, the master issues an acknowledge

(as opposed to a Stop condition in a random read). This

directs the 24XX01 to transmit the next sequentially

addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24XX01 contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation.

7.1

Current Address Read

The 24XX01 contains an address counter that

maintains the address of the last word accessed,

internally incremented by 鈥?/div>

鈥? Therefore, if the previous

access (either a read or write operation) was to

address

, the next current address read operation

would access data from address

n + 1

. Upon receipt of

the slave address with R/W bit set to 鈥?/div>

鈥? the 24XX01

issues an acknowledge and transmits the 8-bit data

word. The master will not acknowledge the transfer but

does generate a Stop condition and the 24XX01

discontinues transmission (Figure 7-1).

7.4

Noise Protection

The 24XX01 employs a V

threshold detector circuit

which disables the internal erase/write logic if the V

is below 1.5V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

7.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must first

be set. This is accomplished by sending the word

address to the 24XX01 as part of a write operation.

Once the word address is sent, the master generates a

Start condition following the acknowledge. This

terminates the write operation, but not before the inter-

nal address pointer is set. The master then issues the

control byte again, but with the R/W bit set to a 鈥?/div>

鈥? The

24XX01 will then issue an acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transfer but does generate a Stop condition and the

24XX01 discontinues transmission (Figure 7-2).

FIGURE 7-1:

CURRENT ADDRESS READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA (n)

SDA LINE

BUS ACTIVITY

铮?/div>

2003 Microchip Technology Inc.

DS21711C-page 9

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