PIC16C621A Datasheet

  • PIC16C621A

  • EPROM-Based 8-Bit CMOS Microcontrollers

  • 2148.18KB

  • 128页

  • Microchip   Microchip

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PIC16C62X
4.3
PCL and PCLATH
4.3.2
STACK
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-14 shows the two
situations for the loading of the PC. The upper example in
the 铿乬ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0>
鈫?/div>
PCH). The lower example in the 铿乬ure
shows how the PC is loaded during a
CALL
or
GOTO
instruction (PCLATH<4:3>
鈫?/div>
PCH).
The PIC16C62X family has an 8 level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a
CALL
instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a
RETURN, RETLW
or a
RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the 铿乺st
push. The tenth push overwrites the second push (and
so on).
Note 1:
Instruction with
PCL as
Destination
ALU result
FIGURE 4-14: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
12
PC
5
PCLATH<4:0>
8
8
7
PCL
0
There are no STATUS bits to indicate
stack over铿俹w or stack under铿俹w
conditions.
There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW
and
RETFIE
instructions, or the vectoring to an
interrupt address.
Note 2:
PCLATH
PCH
12
PC
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
11 10
8
7
PCL
0
GOTO, CALL
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF
PCL).
When doing
a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note
鈥淚mplementing a Table Read"
(AN556).
1998 Microchip Technology Inc.
Preliminary
DS30235G-page 23

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