PIC16C621A Datasheet

IC型号：
PIC16C621A
PDF描述：
EPROM-Based 8-Bit CMOS Microcontrollers
文件大小：
2148.18KB
PDF页数：
128页
芯片厂家：
Microchip

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PIC16C62X

9.5.1

RB0/INT INTERRUPT

9.5.3

PORTB INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if INTEDG bit (OPTION<6>) is set, or fall-

ing, if INTEDG bit is clear. When a valid edge appears

on the RB0/INT pin, the INTF bit (INTCON<1>) is set.

This interrupt can be disabled by clearing the INTE

control bit (INTCON<4>). The INTF bit must be cleared

in software in the interrupt service routine before

re-enabling this interrupt. The RB0/INT interrupt can

wake-up the processor from SLEEP, if the INTE bit was

set prior to going into SLEEP. The status of the GIE bit

decides whether or not the processor branches to the

interrupt vector following wake-up. See Section 9.8 for

details on SLEEP and Figure 9-18 for timing of

wake-up from SLEEP through RB0/INT interrupt.

9.5.2

TMR0 INTERRUPT

An input change on PORTB <7:4> sets the RBIF

(INTCON<0>) bit. The interrupt can be enabled/dis-

abled by setting/clearing the RBIE (INTCON<4>) bit.

For operation of PORTB (Section 5.2).

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt 铿俛g may not get set.

COMPARATOR INTERRUPT

9.5.4

See Section 7.6 for complete description of comparator

interrupts.

An over铿俹w (FFh

鈫?/div>

00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 6.0.

FIGURE 9-16: INT PIN INTERRUPT TIMING

OSC1

CLKOUT 3

INT pin

INTF 铿俛g

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency 2

Inst (PC)

Inst (PC-1)

PC+1

Inst (PC+1)

Inst (PC)

PC+1

鈥?/div>

Dummy Cycle

0004h

Inst (0004h)

Dummy Cycle

0005h

Inst (0005h)

Inst (0004h)

Note 1: INTF 铿俛g is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

TABLE 9-8:

Address

0Bh

0Ch

8Ch

Name

INTCON

PIR1

PIE1

SUMMARY OF INTERRUPT REGISTERS

Bit 7

GIE

鈥?/div>

Bit 6

PEIE

CMIF

CMIE

Bit 5

T0IE

鈥?/div>

Bit 4

INTE

鈥?/div>

Bit 3

RBIE

鈥?/div>

Bit 2

T0IF

鈥?/div>

Bit 1

INTF

鈥?/div>

Bit 0

RBIF

鈥?/div>

Value on POR

Reset

0000 000x

-0-- ----

Value on all

other resets

(1)

0000 000u

-0-- ----

Note1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.

DS30235G-page 56

Preliminary

漏

1998 Microchip Technology Inc.

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