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PIC16C621A Datasheet

  • PIC16C621A

  • EPROM-Based 8-Bit CMOS Microcontrollers

  • 2148.18KB

  • 128页

  • Microchip   Microchip

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PIC16C62X
9.8
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before
SLEEP
was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at V
DD
, or V
SS
, with no external
circuitry drawing current from the I/O pin and the com-
parators and V
REF
should be disabled. I/O pins that are
hi-impedance inputs should be pulled high or low exter-
nally to avoid switching currents caused by 铿俹ating
inputs. The T0CKI input should also be at V
DD
or V
SS
for lowest current consumption. The contribution from
on chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
IHMC
).
Note:
It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
The 铿乺st event will cause a device reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device reset. PD
bit, which is set on power-up is cleared when SLEEP is
invoked. TO bit is cleared if WDT Wake-up occurred.
When the
SLEEP
instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
SLEEP
instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the
SLEEP
instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following
SLEEP
is not desirable, the
user should have an
NOP
after the
SLEEP
instruction.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt 铿俛g bits set, the device will
immediately wakeup from sleep. The sleep
instruction is completely executed.
9.8.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF 铿俛g
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
Inst(PC + 1)
SLEEP
PC+2
PC+2
Inst(PC + 2)
Inst(PC + 1)
Dummy cycle
PC + 2
0004h
Inst(0004h)
Dummy cycle
0005h
Inst(0005h)
Inst(0004h)
Processor in
SLEEP
Interrupt Latency
(Note 2)
T
OST
(2)
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
Note 1:
2:
3:
4:
XT, HS or LP oscillator mode assumed.
T
OST
= 1024T
OSC
(drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
漏
1998 Microchip Technology Inc.
Preliminary
DS30235G-page 59

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