PIC16F871 Datasheet

IC型号：
PIC16F871
PDF描述：
28/40-Pin, 8-Bit CMOS FLASH Microcontrollers
文件大小：
1755.40KB
PDF页数：
172页
芯片厂家：
Microchip

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PIC16F870/871

9.3.2

USART SYNCHRONOUS MASTER

RECEPTION

Once synchronous mode is selected, reception is

enabled by setting either enable bit SREN (RCSTA<5>)

or enable bit CREN (RCSTA<4>). Data is sampled on

the RC7/RX/DT pin on the falling edge of the clock. If

enable bit SREN is set, then only a single word is

received. If enable bit CREN is set, the reception is

continuous until CREN is cleared. If both bits are set,

CREN takes precedence. After clocking the last bit, the

received data in the Receive Shift Register (RSR) is

transferred to the RCREG register (if it is empty). When

the transfer is complete, interrupt flag bit RCIF

(PIR1<5>) is set. The actual interrupt can be enabled/

disabled by setting/clearing enable bit RCIE (PIE1<5>).

Flag bit RCIF is a read only bit, which is reset by the

hardware. In this case, it is reset when the RCREG reg-

ister has been read and is empty. The RCREG is a dou-

ble buffered register (i.e., it is a two deep FIFO). It is

possible for two bytes of data to be received and trans-

ferred to the RCREG FIFO and a third byte to begin

shifting into the RSR register. On the clocking of the last

bit of the third byte, if the RCREG register is still full,

then overrun error bit OERR (RCSTA<1>) is set. The

word in the RSR will be lost. The RCREG register can

be read twice to retrieve the two bytes in the FIFO. Bit

OERR has to be cleared in software (by clearing bit

CREN). If bit OERR is set, transfers from the RSR to

the RCREG are inhibited, so it is essential to clear bit

OERR if it is set. The ninth receive bit is buffered the

same way as the receive data. Reading the RCREG

is essential for the user to read the RCSTA register

before reading RCREG in order not to lose the old

RX9D information.

Steps to follow when setting up a Synchronous Master

Reception:

Initialize the SPBRG register for the appropriate

baud rate. (Section 9.1)

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, then set enable bit RCIE.

5. If 9-bit reception is desired, then set bit RX9.

6. If a single reception is required, set bit SREN.

For continuous reception set bit CREN.

7. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit CREN.

TABLE 9-9:

Address

0Ch

18h

1Ah

8Ch

98h

99h

Name

PIR1

RCSTA

RCREG

PIE1

TXSTA

SPBRG

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Bit 7

PSPIF

(1)

SPEN

PSPIE

(1)

Bit 6

ADIF

RX9

ADIE

TX9

Bit 5

RCIF

SREN

RCIE

TXEN

Bit 4

TXIF

CREN

TXIE

SYNC

Bit 3

鈥?/div>

Bit 2

CCP1IF

FERR

CCP1IE

BRGH

Bit 1

TMR2IF

OERR

TMR2IE

TRMT

Bit 0

TMR1IF

RX9D

TMR1IE

TX9D

Value on:

POR,

BOR

0000 -000

0000 -00x

0000 0000

0000 -000

0000 -010

0000 0000

Value on all

other Resets

0000 -000

0000 -00x

0000 0000

0000 -000

0000 -010

0000 0000

USART Receive Register

CSRC

Baud Rate Generator Register

Legend:

= unknown,

= unimplemented read as '0'. Shaded cells are not used for synchronous master reception.

Note 1:

Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.

FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT pin

RC6/TX/CK pin

Write to

bit SREN

SREN bit

CREN bit

RCIF bit

(interrupt)

Read

RXREG

鈥?鈥?/div>

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

鈥?鈥?/div>

Note:

Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.

漏

1999 Microchip Technology Inc.

Preliminary

DS30569A-page 75

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