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PIC16F871 Datasheet

  • PIC16F871

  • 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

  • 1755.40KB

  • 172页

  • Microchip   Microchip

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PIC16F870/871
11.10
Interrupts
The PIC16F870/871 family has up to 11 sources of
interrupt. The interrupt control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt鈥檚 flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The 鈥渞eturn from interrupt鈥?instruction,
RETFIE,
exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 11-9: INTERRUPT LOGIC
EEIF
EEIE
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
GIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
The following table shows which devices have which interrupts.
Device
PIC16F870
PIC16F871
T0IF
Yes
Yes
INTF
Yes
Yes
RBIF
Yes
Yes
PSPIF
-
Yes
ADIF
Yes
Yes
RCIF
Yes
Yes
TXIF
Yes
Yes
CCP1IF TMR2IF TMR1IF
Yes
Yes
Yes
Yes
Yes
Yes
EEIF
Yes
Yes
漏
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 99

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