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3803 Datasheet

  • 3803

  • SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

  • 1618.05KB

  • RENESAS

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3803 Group (Spec.L)
3. S
RDY3
output of reception side
鈥?Note
When signals are output from the S
RDY3
pin on the reception
side by using an external clock in the clock synchronous serial
I/O mode, set all of the receive enable bit, the S
RDY3
output
enable bit, and the transmit enable bit to 鈥?鈥?(transmit
enabled).
4. Setting serial I/O3 control register again
鈥?Note
Set the serial I/O3 control register again after the transmission
and the reception circuits are reset by clearing both the
transmit enable bit and the receive enable bit to 鈥?鈥?
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to 鈥?鈥?/div>
7. Transmit interrupt request when transmit enable bit is set
鈥?Note
When using the transmit interrupt, take the following
sequence.
1. Set the serial I/O3 transmit interrupt enable bit to 鈥?鈥?(dis-
abled).
2. Set the transmit enable bit to 鈥?鈥?
3. Set the serial I/O3 transmit interrupt request bit to 鈥?鈥?after
1 or more instruction has executed.
4. Set the serial I/O3 transmit interrupt enable bit to 鈥?鈥?/div>
(enabled).
鈥?Reason
When the transmit enable bit is set to 鈥?鈥? the transmit buffer
empty flag and the transmit shift register shift completion flag
are also set to 鈥?鈥? Therefore, regardless of selecting which
timing for the generating of transmit interrupts, the interrupt
request is generated and the transmit interrupt request bit is set
at this point.
Set the bits 0 to 3 and bit 6 of
the serial I/O3 control register
Can be set with the
LDM
instruction at
the same time
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to 鈥?鈥?/div>
5.Data transmission control with referring to transmit shift
register completion flag
鈥?Note
After the transmit data is written to the transmit buffer register,
the transmit shift register completion flag changes from 鈥?鈥?to
鈥?鈥?with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after
writing the data to the transmit buffer register, note the delay.
6. Transmission control when external clock is selected
鈥?Note
When an external clock is used as the synchronous clock for
data transmission, set the transmit enable bit to 鈥?鈥?at 鈥淗鈥?of
the S
CLK3
input level. Also, write data to the transmit buffer
register at 鈥淗鈥?of the S
CLK
input level.
Rev.1.00 Apr 2, 2007
REJ03B0212-0100
Page 56 of 117

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