3803 Group (Spec.L)
b7
b0
PWM control register
(PWMCON: address 002B
16
)
PWM function enable bit
0 : PWM disabled
1 : PWM enabled
Count source selection bit
0 : f(X
IN
) (f(X
CIN
) at low-speed mode)
1 : f(X
IN
)/2 (f(X
CIN
)/2 at low-speed mode)
Not used
(return 鈥?鈥?when read)
Fig 51. Structure of PWM control register
A
PWM output
T
PWM register
write signal
PWM prescaler
write signal
B
C
B
C
= T2
T
T
T2
(Changes 鈥淗鈥?term from 鈥淎鈥?to 鈥?B鈥?)
(Changes PWM period from 鈥淭鈥?to 鈥淭2鈥?)
When the contents of the PWM register or PWM prescaler have changed,
the PWM output will change from the next period after the change.
Fig 52. PWM output timing when PWM register or PWM prescaler is changed
<Notes>
The PWM starts after the PWM function enable bit is set to enable and 鈥淟鈥?level is output from the PWM pin.
The length of this 鈥淟鈥?level output is as follows:
n
+
1
-
----------------------
sec
2
脳
f
(
X
IN
)
n
+
1
---------------
sec
-
f
(
X
IN
)
(Count source selection bit = 0, where n is the value set in the prescaler)
(Count source selection bit = 1, where n is the value set in the prescaler)
Rev.1.00 Apr 2, 2007
REJ03B0212-0100
Page 58 of 117