ADSP-218xN Series
Clock Signals and Reset
Table 15. Clock Signals and Reset
Parameter
Min
Max
Unit
Timing Requirements:
t
CKI
CLKIN Period
t
CKIL
CLKIN Width Low
t
CKIH
CLKIN Width High
Switching Characteristics:
t
CKL
CLKOUT Width Low
CLKOUT Width High
t
CKH
t
CKOH
CLKIN High to CLKOUT High
Control Signals Timing Requirements:
t
RSP
RESET Width Low
t
MS
Mode Setup before RESET High
t
MH
Mode Hold after RESET High
1
25
8
8
0.5t
CK
鈥?3
0.5t
CK
鈥?3
0
5t
CK
1
7
5
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including
crystal oscillator start-up time).
t
CKI
t
CKIH
CLKIN
t
CKIL
t
CKOH
t
CKH
CLKOUT
t
CKL
MODE A D
t
MS
RESET
t
MH
t
RSP
Figure 24. Clock Signals and Reset
REV. 0
鈥?7鈥?/div>
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